The invention relates generally to graphics processing and more particularly to a graphics processing system that uses a logic enhanced memory circuit and method therefore.
Computer systems often include dedicated video graphics processing hardware in order to offload such processing from the central processor. The dedicated video graphics processing hardware typically uses a frame buffer to store the image data corresponding to graphics primitives that have been rendered. Data in the frame buffer is fetched and converted into a display signal that is provided to a display on which the image is presented to the viewer.
Rendering video graphic primitives to the frame buffer for three-dimensional (3D) applications typically involves fetching current pixel information from the frame buffer for a comparison operation with pixel fragments generated from the video graphics primitives received. The comparison determines if the positioning of the fragment with respect to the pixel data already in the frame buffer requires the color and Z (depth coordinate) data in the frame buffer to be updated. If the comparison indicates that the fragment can be discarded (e.g. the fragment lies behind the current pixel data and therefore is not visible), no information need be written back to the frame buffer. However, if the color data associated with the fragment is to replace that currently stored in the frame buffer, or for blending of the fragments color and the color from the frame buffer is required, the resulting color and Z data must be written back to the frame buffer.
In a typical video graphics processing system, the frame buffer, which often requires a significant amount of memory, is implemented as a stand-alone memory circuit separate from the graphics processing circuit. Thus, the frame buffer may be stored within a conventional dynamic random access memory (DRAM) integrated circuit, or other stand-alone memory circuit. Having to repeatedly retrieve data from this separate integrated circuit and often write data back to this separate integrated circuit based on pixel fragments generated can require a large amount of bandwidth over the bus coupling the memory that includes the frame buffer to the graphics processing circuit. As the pixel processing rates associated with graphics processing circuits increase, a communication bottleneck between the graphics chip that performs the rendering operations and the memory structure that stores the frame buffer can result. As such, overall system performance can be limited based on the bandwidth available over the bus connecting these two circuits.
Some prior art graphics processing systems have proposed moving portions of the render backend block that performs the comparison and blending operations into the memory circuit that stores the frame buffer. However, these prior art systems do not provide an efficient data transfer means between the graphics processing circuit and the memory circuit that includes the frame buffer such that the available bandwidth between these two circuits can be efficiently utilized. As such, bandwidth limitations still present a bottleneck such that the pixel processing rates demanded by the video graphics processing systems cannot be met.